Power control and power reduction are important aspects of implementing an integrated circuit device, such as a programmable logic device (PLD) or an application specific integrated circuit (ASIC). Dynamic power gating control may be implemented in integrated circuits where a floor plan is divided into multiple power domains, with individual power control signals provided for each domain. The individual power domains can be turned OFF/ON by asserting the power control signals. However, various design constraints need to be satisfied for power gating control signals to provide a robust power gating solution. For example, supply bounce and in-rush currents must be controlled in the sleep and wake-up sequencing of the power domains.
An example of an application for global power gating is a redundant line card in an integrated circuit, such as a PLD. As the redundant line card becomes functional in response to an external interrupt, the entire fabric needs to wake up with well-defined in-rush current and supply bounce. This requires a dedicated staggered control signal in the user design, which powers up sets of fabric/logic in the design. However, conventional solutions of power sleep control (PSC) that distribute a dedicated staggered power gating signal are costly, because it is necessary to route this signal and have dedicated buffers for staggering the control signal.